asahi kasei [akd4220-a] 2006/06 - 1 - general description akd4220-a is an evaluation board for AK4220 that has various 7:3 audio and 6:3 video switches. this board can achieve the interface with av systems via rca connectors. ? ordering guide akd4220-a --- AK4220 evaluation board 10-wire flat cable for connection with pr inter port of pc (ibm-at compatible machine), control software for AK4220, driver for control software on windows 2000/xp are packed with this. control software does not work on windows nt windows 2000/xp needs an installation of driver. windows 95/98/me does not need an installation of driver. function ? rca connectors for analog audio: 7 inputs 3 outputs ? rca connectors for video: 6 inputs, 3 outputs ? 10-pin header for i 2 c/4-wire serial control AK4220 gnd1 lout1 rout1 lout2 avdd lin+1 rin+1 lin+2 gnd3 lin+3 gnd2 rout2 +12v vvdd1 dvdd rin+2 gnd6 lin+7 rin+6 gnd7 lin+4 rin+3 rin+4 gnd5 lin+5 gnd4 rin+5 lin+6 rin+7 vin3 vin4 vin5 vin6 vin1 vin2 lout3 rout3 vout1 vout2 vout3 reg 5v digital logic d3.3v * o q v u d j s d v j u t 0 v u q v u d j s d v j u t vvdd2 avdd vvdd1 d5v reg 3.3v dvdd figure 1. akd4220-a block diagram * circuit diagram and pcb layout are attached at the end of this manual. a k4220 evaluation board rev.0 a kd4220- a
asahi kasei [akd4220-a] 2006/06 - 2 - evaluation board manual ? operation sequence 1) set up power supply lines. name of jack color of jack voltage used for open / connect default setting +12v green +12v regulator (t1) should be always connected when power supply lines are supplied from regulator of t1. in this case ?jp9 (reg)? is set to short. +12v avdd red +5v avdd of AK4220 should be always connected when avdd is not supplied from regulator of t1. in this case ?jp9 (reg)? is set to open. open vvdd1 bule +5v vvdd1 of AK4220 should be always connected when avdd is not supplied from regulator of t1. in this case ?jp10 (vvdd1)? is set to open. open d5v red +5v regulator (t2) should be always connected when jp2(dvdd_sel) is set to dvdd side. can be open when jp2(dvdd_sel) is set to reg side. open dvdd orange +3.3v dvdd of AK4220 should be always connected when dvdd is not supplied from regulator of t1 and t2. in this case ?jp15 (dvdd)? is set to open. open d3.3v orange +3.3v digital logic should be always connected when d3.3v is not supplied from regulator of t1 and t2. in this case ?jp13 (d3.3v)? is set to open. open agnd black 0v analog ground should be always connected. 0v vvss black 0v analog ground should be always connected. 0v dgnd black 0v digital ground should be always connected, when jp1 (gnd) is set to open. 0v table 1. set up the power supply lines (note) each supply line should be distributed from the power supply unit. 2) set-up jumper pins and dip switches. (see the followings.) 3) power on. AK4220 should be reset once bringing sw2 (pdn) to ?l? upon power-up.
asahi kasei [akd4220-a] 2006/06 - 3 - ? set up jumper pins 1. jp1 (gnd) : analog ground and digital ground open : separated. short : common. (the connector ?dgnd? can be open.) 2. jp9 (reg) : avdd, vvdd1 of the AK4220, and regulator of t2 (ta48m033f) open : avdd is supplied from ?avdd ? jack. (?+12v? jack should be open) short : avdd is supplied from regulator of t1 (njm78m05fa). < default > 3. jp16 (avdd) : avdd of the AK4220 open : avdd is supplied from ?avdd ? jack. short : avdd is supplied from regulator of t1 (njm78m05fa). (?avdd? jack should be open) < default > 4. jp10 (vvdd1) : vvdd1 of the AK4220 open : vvdd1 is supplied from ?vvdd1 ? jack. short : vvdd1 is supplied from regulator of t1 (njm78m05fa). (?vvdd1? jack should be open) < default > 5. jp11 (d-a) : regulator of t2 (ta48m033f) open : regulator of t2 (ta48m033f) is supplied from ?d5v ? jack. short : regulator of t2 (ta48m033f) is supplied from regulator of t1 (njm78m05fa). (?d5v? jack should be open) < default > 6. jp15 (dvdd) : dvdd of the AK4220 open : dvdd is supplied from ?dvdd ? jack. short : dvdd is supplied from regulator of regulator of t2 (ta48m033f). (?dvdd? jack should be open) < default > 7. jp13 (d3.3v) : power of digital logic open : d3.3v is supplied from ?d3.3v ? jack. short : d3.3v is supplied from regulator of regulator of t2 (ta48m033f). (?d3.3v? jack should be open) < default > 8. jp12 (vvdd2) : should be open.
asahi kasei [akd4220-a] 2006/06 - 4 - ? set up dip switches sw1 setting for i2c of AK4220 pin no. pin name on (?h?,?1?) / off (?l?,?0?) default 1 i2c control mode select on (?h?, ?1?) 2 cad1 chip address select (note1) off (?l?, ?0?) 3 cad0 chip address select (note1) off (?l?, ?0?) table 2. sw1 setting for i2c of AK4220 (note1) chip address is selected by ca d1, cad0 pin (cad10=?00?,?01?,?10?,?11? ) ? the function of the toggle sw [sw2] (pdn): resets the AK4220. keep ?h? during normal operation. ? indication for led [le1] (int): monitor int0 pin of the AK4220. led turns on when channel dependent audio input detect circuit and video signal detect circuit of the AK4220. [le2 6] (q0 4): monitor q0 4 pin of the AK4220.
asahi kasei [akd4220-a] 2006/06 - 5 - ? serial control the AK4220 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect printer port (parallel port) of pc and port2 (ctrl) of akd4220-a by 10-wire flat cable (packed with akd4220-a). take care of the direction of 10-pin connector and 10-pin header. the control software packed with this evaluation board supports 4-wire serial control only. connect cdto/sda cclk/scl cdti/sda 10-pin header 10-pin connector 10-wire flat cable pc akd4220-a csn 56 110 port2 ctrl red figure 2. 10-wire flat cable, 10-pin connector, and 10-pin header (1) 4-wire serial control mode the jumper pins should be set to the following. (2) i 2 c-bus control mode the jumper pins should be set to the following. jp8 i2c jp8 i2c
asahi kasei [akd4220-a] 2006/06 - 6 - ? input / output circuit & set-up jumper pin for input / output circuits (1) audio input circuit gnd1, lin+1, rin+1 gnd7, lin+7, rin+7 input circuits 1 2 3 4 5 j4 lin+1 r10 (open) lin+1 1 2 3 4 5 j7 rin+1 r13 (open) rin+1 r73 (short) r74 (short) r75 (short) + c18 0.47u 1 2 3 4 5 j1 gnd1 + c21 0.47u r7 (open) + c24 0.47u gnd1 figure 3. gnd, lin+, rin+ input circuit (2) audio output circuit lout1/rout1 lout3/rout3 output circuits r28 300 + c39 10u 1 2 3 4 5 j22 lout1 lout1 r29 300 + c40 10u 1 2 3 4 5 j23 rout1 rout1 r94 22k r95 22k figure 4. lout/rout output circuit
asahi kasei [akd4220-a] 2006/06 - 7 - (3)video input circuit vin1 vin6 input circuits c64 0.1u r58 (short) r61 75 vin1 1 2 3 4 5 j28 vin1 figure 5. vin input circuit (4)video output circuit vout1 vout3 output circuits 1 2 3 4 5 j34 vout1 vfb1 r70 75 vout1 + c45 2.2u + c70 100u jp2 sag1-1 1 0 0 1 jp3 sag1-2 figure 6. vout output circuit (4-1) ?dc output? is output from j34, j35 and j36 connector. (sagn bit = 1) (4-2) ?sag trimming circuit ? is output from j 34, j35 and j36 connector. (sagn bit = 0) jp2/jp4/jp6 sag1-1/sag2-1/sag3-1 10 jp3/jp5/jp7 sag1-2/sag2-2/sag3-2 10 jp2/jp4/jp6 sag1-1/sag2-1/sag3-1 10 jp3/jp5/jp7 sag1-2/sag2-2/sag3-2 10
asahi kasei [akd4220-a] 2006/06 - 8 - control software manual ? set-up of evaluation board and control software 1. set up the akd4220-a according to previous term. 2. connect ibm-at compatible pc with akd4220-a by 10-line type flat cable (packed with akd4220-a). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not needed. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?akd4220-a evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd4220-a.exe? to set up the control program. 5. then please evaluate according to the follows. ? operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. ? explanation of each buttons 1. [port reset]: set up the usb interface board (akdusbif-a). 2. [write default]: initialize the register of AK4220. 3. [all write]: write all registers that is currently displayed. 4. [function1]: dialog to write data by keyboard operation. 5. [function2]: dialog to write data by keyboard operation. 6. [function3]: the sequence of register setting can be set and executed. 7. [function4]: the sequence that is created on [function3] can be assigned to buttons and executed. 8. [function5]: the register setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save]: save the current register setting. 10. [open]: write the saved values to all register. 11. [write]: dialog to write data by mouse operation. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
asahi kasei [akd4220-a] 2006/06 - 9 - ? explanation of each dialog 1. [write dialog]: dialog to write data by mouse operation there are dialogs corresponding to each register. click the [write] button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. when writing the input data to AK4220, click [ok] button. if not, click [cancel] button. 2. [function1 dialog]: dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. when writing the input data to AK4220, click [ok] button. if not, click [cancel] button. 3. [function2 dialog]: dialog to evaluate att of vol control address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is written to AK4220 by this interval. step box: data changes by this step. mode select box: with checking this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 without checking this check box, data reaches end data, but does not return to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 when writing the input data to AK4220, click [ok] button. if not, click [cancel] button.
asahi kasei [akd4220-a] 2006/06 - 10 - 4. [save] and [open] 4-1. [save] save the current register setting data. the extension of file name is ?akr?. (operation flow) (1) click [save] button. (2) set the file name and push [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting data saved by [save] is written to AK4220. the file type is the same as [save]. (operation flow) (1) click [open] button. (2) select the file (*.akr) and click [open] button.
asahi kasei [akd4220-a] 2006/06 - 11 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. (2) set the control sequence. set the address, data and interval time. set ?-1? to the address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the [function3] window. the extension of file name is ?aks?. figure 1. window of [f3]
asahi kasei [akd4220-a] 2006/06 - 12 - 6. [function4 dialog] the sequence that is created on [function3] can be assigned to buttons and executed. when [f4] button is clicked, the window as shown in figure 2 opens. figure 2. [f4] window
asahi kasei [akd4220-a] 2006/06 - 13 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the sequence file (*.aks). the sequence file name is displayed as shown in figure 3 . figure 3. [f4] window(2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save]: the sequence file names can assign be saved. the file name is *.ak4. [open]: the sequence file names assign that are saved in *.ak4 are loaded. 6-3. note (1) [function4] doesn't support the pause function of sequence function. (2) all files need to be in same folder used by [save] and [open] function on right side. (3) when the sequence is changed in [function3], the file should be loaded again in order to reflect the change.
asahi kasei [akd4220-a] 2006/06 - 14 - 7. [function5 dialog] the register setting that is created by [save] function on main window can be assigned to buttons and executed. when [f5] button is clicked, the following window as shown in figure 4 opens. figure 4. [f5] window 7-1. [open] buttons on left side and [write] button ( 1) click [open] button and select the register setting file (*.akr). (2) click [write] button, then the register setting is executed. 7-2. [save] and [open] buttons on right side [save]: the register setting file names assign can be saved. the file name is *.ak5 . [open]: the register setting file names assign that are saved in *.ak5 are loaded. 7-3. note (1) all files need to be in same folder used by [save] and [open] function on right side. (2) when the register setting is changed by [save] button in main window, the file should be loaded again in order to reflect the change.
asahi kasei [akd4220-a] 2006/06 - 15 - measurement results ? audio [measurement condition] ? measurement unit : audio precision system two cascade ? bw : 10hz 20khz ? power supply : avdd=5v, vvdd1=5v, vvdd2=5v, dvdd=3v ? temperature : room ? measurement signal line path: lin+1/rin+1 lout/rout parameter input signal measurement filter results [db] s/(n+d) at 1vrms output 1khz, 0dbv 20klpf 93.2 / 93.1 dr 1khz, -60dbv 22klpf, a-weighted 96.2 / 96.2 s/n off 22klpf, a-weighted 96.2 / 96.1 plots figure 1-1. fft (1khz, 0dbv input) at 1vrms output figure 1-2. fft (1khz, -60dbv input) figure 1-3. fft (noise floor) figure 1-4. thd+n vs. input level (fin=1khz) figure 1-5. thd+n vs. fin (input level=0dbfs) figure 1-6. linearity (fin=1khz) figure 1-7. frequency response (input level=0dbv) figure 1-8. crosstalk (input level=0dbv)
asahi kasei [akd4220-a] 2006/06 - 16 - ? video [measurement condition] ? signal generator : sony tectonics tg2000 ? measurement unit : sony tectonics vm700t ? power supply : avdd=5v, vvdd1=5v, vvdd2=5v, dvdd=3v ? temperature : room ? measurement signal line path: vin1 vout1 parameter measurement conditions results unit s/n input = 0% flat field filter = uni-weighted, bw= 15khz to 5mhz sag = 1 72.4 db crosstalk input = 100%red(encrc), measured at vout -74.0 db dg input = modulated lamp sag = 1 0.22 % dp input = modulated lamp sag = 1 0.91 deg. plots figure 2-1. noise spectrum (input=0%flat field, bw=15khz to 5mhz, uni weighted, sag=1) figure 2-2. frequency response (input= multi burst, sag=1) figure 2-3 crosstalk (input= 100% red (vin1), measured at vout1) figure 2-4 crosstalk (input= 100% red (vin2), measured at vout1) figure 2-5 dg, dp (input= modulated lamp, sag=1)
asahi kasei [akd4220-a] 2006/06 - 17 - plots (audio) akm 11/17/05 10:47:28 AK4220 fft lin1/rin1-->lout1/rout1 input=0dbv -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b v 20 20k 50 100 200 500 1k 2k 5k 10k hz figure1-1. fft (fin=1khz input level=0dbv) akm 11/17/05 10:55:52 AK4220 fft lin1/rin1-->lout1/rout1 input=-60dbv -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b v 20 20k 50 100 200 500 1k 2k 5k 10k hz figure-1-2. fft (fin=1khz input level=-60dbv)
asahi kasei [akd4220-a] 2006/06 - 18 - akm 11/17/05 11:18:13 AK4220 fft lin1/rin1-->lout1/rout1 input=no signal -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b v 20 20k 50 100 200 500 1k 2k 5k 10k hz figure1-3. fft (noise floor) akm 11/17/05 11:05:06 AK4220 lin1/rin1-->lout1/rout1 thd vs.input level fin=1khz -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b r a -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbv figure1-4. thd+n vs. input level (fin=1khz)
asahi kasei [akd4220-a] 2006/06 - 19 - akm 11/17/05 11:13:51 AK4220 lin1/rin1-->lout1/rout1 thd vs.input frequency input=0db -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure1-5. thd+n vs. input frequency (input level=0dbv) akm 11/17/05 11:22:34 AK4220 lin1/rin1-->lout1/rout1 linearity fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbv -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure1-6.linearity (fin=1khz)
asahi kasei [akd4220-a] 2006/06 - 20 - akm 05/18/06 13:15:12 AK4220 lin+1/rin+1-->lineout frequency response input=0dbv last.at2 -1 +1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 +0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz figure1-7. frequency response (input level=0dbv) figure1-8. crosstalk (input level=0dbv)
asahi kasei [akd4220-a] 2006/06 - 21 - plots(video) figure 2-1. noise spectrum (input=0%flat field, bw=15khz to 5mhz, uni weighted, sag=1) figure 2-2. frequency response (input= multi burst, sag=1)
asahi kasei [akd4220-a] 2006/06 - 22 - figure 2-4 crosstalk (input= 100% red (vin1), measured at vout1) figure 2-4 crosstalk (input= 100% red (vin2), measured at vout1)
asahi kasei [akd4220-a] 2006/06 - 23 - figure 2-5 dg, dp (input= modulated lamp, sag=1)
asahi kasei [akd4220-a] 2006/06 - 24 - revision history important notice ? these products and their specificati ons are subject to change without noti ce. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems co ntaining them, may require an export license or other official approval under the law and regulations of th e country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the repres entative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of li fe or in significant injury or damage to person or property. (b) a critical component is one whos e failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very hi gh standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that pa rty in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all resp onsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. date (yy/mm/dd) manual revision board revision reason contents 06/06/12 km083400 0 first edition
5 5 4 4 3 3 2 2 1 1 d d c c b b a a avdd_in gnd2 pdn vin6 rout1 rin+6 dvdd_in vvdd1_in cdto/cad0 lin+7 lin+6 lin+5 lin+4 lin+3 lin+2 gnd7 gnd6 gnd5 gnd4 gnd3 rin+5 rin+4 rin+3 rin+2 csn/cad1 cclk/scl cdti/sda int q0 q1 q2 q3 q4 rin+7 vin1 vin2 vin3 vin4 vin5 vvdd1_in lout1 gnd1 rin+1 lin+1 lout2 lout3 rout2 rout3 i2c vout1 vout2 vout3 title size document number rev date: sheet of AK4220 0 akd4220-a a2 16 title size document number rev date: sheet of AK4220 0 akd4220-a a2 16 title size document number rev date: sheet of AK4220 0 akd4220-a a2 16 analog ground digital ground vvss 00 1 100 1 1 0 0 1 1 + c9 2.2u + c9 2.2u r3 51 r3 51 c10 0.1u c10 0.1u + c8 100u + c8 100u r2 51 r2 51 + c17 2.2u + c17 2.2u jp6 sag3-1 jp6 sag3-1 + c16 100u + c16 100u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cn1 64pin_1 cn1 64pin_1 jp7 sag3-2 jp7 sag3-2 r5 51 r5 51 c11 0.1u c11 0.1u + c2 2.2u + c2 2.2u c1 0.1u c1 0.1u + c3 10u + c3 10u + c13 10u + c13 10u r4 51 r4 51 + c5 1u + c5 1u 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 cn2 64pin_4 cn2 64pin_4 + c7 10u + c7 10u + c15 2.2u + c15 2.2u + c12 10u + c12 10u rin+7 1 pdn 2 cad1/csn 3 scl/cclk 4 sda/cdti 5 cad0/cdto 6 int 7 q0 8 q1 9 q2 10 q3 11 q4 12 dvdd 13 dvss 14 vout1 15 vfb1 16 test 17 vout2 18 vfb2 19 vvdd2 20 vout3 21 vfb3 22 vvss2 23 vin1 24 vvss3 25 vin2 26 vvdd1 27 vin3 28 vvss1 29 vin4 30 iicn 31 vin5 32 vin6 33 avdd 34 r 35 mutet 36 vcom 37 avss 38 lout1 39 rout1 40 lout2 41 rout2 42 lout3 43 rout3 44 gnd1 45 lin+1 46 rin+1 47 gnd2 48 lin+2 49 rin+2 50 gnd3 51 lin+3 52 rin+3 53 gnd4 54 lin+4 55 rin+4 56 gnd5 57 lin+5 58 rin+5 59 gnd6 60 lin+6 61 rin+6 62 gnd7 63 lin+7 64 u1 AK4220 u1 AK4220 jp4 sag2-1 jp4 sag2-1 jp5 sag2-2 jp5 sag2-2 r1 51 r1 51 jp1 gnd jp1 gnd jp3 sag1-2 jp3 sag1-2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cn3 64pin_3 cn3 64pin_3 jp2 sag1-1 jp2 sag1-1 c6 0.1u c6 0.1u r6 12k r6 12k + c14 100u + c14 100u c4 0.1u c4 0.1u 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cn4 64pin_2 cn4 64pin_2
5 5 4 4 3 3 2 2 1 1 d d c c b b a a gnd1 lin+1 rin+1 lin+2 rin+2 gnd2 lin+3 rin+3 gnd3 lin+4 rin+4 gnd4 lin+5 rin+5 gnd5 lin+6 rin+6 gnd6 lin+7 rin+7 gnd7 title size document number rev date: sheet of analog input circuit 0 akd4220-a a3 26 tuesday, september 13, 2005 title size document number rev date: sheet of analog input circuit 0 akd4220-a a3 26 tuesday, september 13, 2005 title size document number rev date: sheet of analog input circuit 0 akd4220-a a3 26 tuesday, september 13, 2005 r15 (open) r15 (open) + c26 0.47u + c26 0.47u 1 2 3 4 5 j12 gnd6 j12 gnd6 + c37 0.47u + c37 0.47u r20 (open) r20 (open) 1 2 3 4 5 j15 lin+6 j15 lin+6 r87 (short) r87 (short) r74 (short) r74 (short) 1 2 3 4 5 j21 rin+7 j21 rin+7 1 2 3 4 5 j14 lin+5 j14 lin+5 + c36 0.47u + c36 0.47u r79 (short) r79 (short) 1 2 3 4 5 j11 gnd5 j11 gnd5 r19 (open) r19 (open) + c23 0.47u + c23 0.47u r80 (short) r80 (short) + c24 0.47u + c24 0.47u r89 (short) r89 (short) 1 2 3 4 5 j18 rin+6 j18 rin+6 1 2 3 4 5 j13 lin+4 j13 lin+4 r85 (short) r85 (short) r73 (short) r73 (short) + c20 0.47u + c20 0.47u r12 (open) r12 (open) r81 (short) r81 (short) 1 2 3 4 5 j10 gnd4 j10 gnd4 + c33 0.47u + c33 0.47u + c27 0.47u + c27 0.47u + c21 0.47u + c21 0.47u 1 2 3 4 5 j17 rin+5 j17 rin+5 r93 (short) r93 (short) r25 (open) r25 (open) 1 2 3 4 5 j6 lin+3 j6 lin+3 r82 (short) r82 (short) + c35 0.47u + c35 0.47u + c34 0.47u + c34 0.47u 1 2 3 4 5 j5 lin+2 j5 lin+2 + c30 0.47u + c30 0.47u 1 2 3 4 5 j3 gnd3 j3 gnd3 1 2 3 4 5 j16 rin+4 j16 rin+4 r18 (open) r18 (open) r27 (open) r27 (open) r14 (open) r14 (open) + c18 0.47u + c18 0.47u + c32 0.47u + c32 0.47u + c31 0.47u + c31 0.47u + c25 0.47u + c25 0.47u 1 2 3 4 5 j9 rin+3 j9 rin+3 r7 (open) r7 (open) r78 (short) r78 (short) r17 (open) r17 (open) 1 2 3 4 5 j8 rin+2 j8 rin+2 r92 (short) r92 (short) r8 (open) r8 (open) 1 2 3 4 5 j2 gnd2 j2 gnd2 1 2 3 4 5 j1 gnd1 j1 gnd1 + c29 0.47u + c29 0.47u + c28 0.47u + c28 0.47u r83 (short) r83 (short) r24 (open) r24 (open) r88 (short) r88 (short) r13 (open) r13 (open) r16 (open) r16 (open) + c22 0.47u + c22 0.47u r75 (short) r75 (short) r86 (short) r86 (short) r77 (short) r77 (short) 1 2 3 4 5 j7 rin+1 j7 rin+1 r23 (open) r23 (open) (short) (short) r90 (short) r90 (short) r26 (open) r26 (open) r11 (open) r11 (open) r91 (short) r91 (short) + c19 0.47u + c19 0.47u r9 (open) r9 (open) r22 (open) r22 (open) r84 (short) r84 (short) r10 (open) r10 (open) + c38 0.47u + c38 0.47u 1 2 3 4 5 j19 gnd7 j19 gnd7 1 2 3 4 5 j20 lin+7 j20 lin+7 r21 (open) r21 (open) 1 2 3 4 5 j4 lin+1 j4 lin+1
5 5 4 4 3 3 2 2 1 1 d d c c b b a a lout1 rout1 lout2 rout2 lout3 rout3 title size document number rev date: sheet of analog output circuit 0 akd4220-a a3 36 tuesday, september 13, 2005 title size document number rev date: sheet of analog output circuit 0 akd4220-a a3 36 tuesday, september 13, 2005 title size document number rev date: sheet of analog output circuit 0 akd4220-a a3 36 tuesday, september 13, 2005 + c40 10u + c40 10u 1 2 3 4 5 j26 lout3 j26 lout3 r28 300 r28 300 r99 22k r99 22k r97 22k r97 22k r95 22k r95 22k 1 2 3 4 5 j23 rout1 j23 rout1 r31 300 r31 300 + c42 10u + c42 10u r33 300 r33 300 1 2 3 4 5 j22 lout1 j22 lout1 1 2 3 4 5 j25 rout2 j25 rout2 + c44 10u + c44 10u r30 300 r30 300 r98 22k r98 22k r96 22k r96 22k 1 2 3 4 5 j27 rout3 j27 rout3 + c41 10u + c41 10u r32 300 r32 300 + c39 10u + c39 10u r29 300 r29 300 r94 22k r94 22k 1 2 3 4 5 j24 lout2 j24 lout2 + c43 10u + c43 10u
a a b b c c d d e e e e d d c c b b a a d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in d3.3v_in cdto/cad0 cad1 i2c_h cad0 pdn int q0 q1 q2 q3 q4 csn/cad1 cclk/scl cdti/sda d3.3v_in d3.3v_in d3.3v_in i2c_h cad1 cad0 i2c title size document number rev date: sheet of logic 0 akd4220-a a3 46 friday, may 19, 2006 title size document number rev date: sheet of logic 0 akd4220-a a3 46 friday, may 19, 2006 title size document number rev date: sheet of logic 0 akd4220-a a3 46 friday, may 19, 2006 lh cclk/sci cdto/sda(ack) cdti/sda csn int q0 q1 q2 q3 q4 cad0 cad1 i2c 1 2 3 4 5 6 sw1 i2c mode sw1 i2c mode r50 10k r50 10k r51 470 r51 470 le4 q2 le4 q2 r43 1k r43 1k le5 q3 le5 q3 le1 int le1 int 9 8 14 7 u3d 74hcu04 u3d 74hcu04 1 2 3 4 5 6 7 8 9 10 port1 q/int port1 q/int r44 1k r44 1k r40 1k r40 1k 3 4 14 7 u6b 74hc14 u6b 74hc14 1 2 14 7 u4a 74hc04 u4a 74hc04 le3 q1 le3 q1 c58 0.1u c58 0.1u 11 10 14 7 u3e 74hcu04 u3e 74hcu04 1 2 14 7 u3a 74hcu04 u3a 74hcu04 c46 0.1u c46 0.1u 1a 2 1y 4 1b 3 2a 5 2y 7 2b 6 3a 11 3y 9 3b 10 4a 14 4y 12 4b 13 a/b 1 g 15 vcc 16 gnd 8 u5 74lvc157 u5 74lvc157 r42 1k r42 1k 5 6 14 7 u3c 74hcu04 u3c 74hcu04 r48 10k r48 10k 2 1 3 sw2 pdn sw2 pdn jp8 i2c jp8 i2c r35 51 r35 51 r34 51 r34 51 r54 10k r54 10k r53 51 r53 51 r36 51 r36 51 1 2 14 7 u6a 74hc14 u6a 74hc14 r46 10k r46 10k r37 51 r37 51 1 2 14 7 u7a 74lvc07 u7a 74lvc07 r38 51 r38 51 le6 q4 le6 q4 3 2 1 rp2 47k rp2 47k r39 51 r39 51 r45 1k r45 1k 13 12 14 7 u3f 74hcu04 u3f 74hcu04 c47 0.1u c47 0.1u 6 5 4 3 2 1 rp1 10k rp1 10k le2 q0 le2 q0 r49 470 r49 470 r41 1k r41 1k r47 470 r47 470 2 1 d1 hsu119 d1 hsu119 3 4 14 7 u3b 74hcu04 u3b 74hcu04 1 2 3 4 5 6 7 8 9 10 port2 ctrl port2 ctrl r52 10k r52 10k r100 3.9k r100 3.9k
5 5 4 4 3 3 2 2 1 1 d d c c b b a a +12v dvdd avdd vvdd1 vvdd2 d5v d3.3v +12v avdd vvdd1 dvdd d3.3v vvdd2 d5v d3.3v_in avdd_in dvdd_in vvdd1_in vvdd2_in d3.3v_in title size document number rev date: sheet of power supply 0 akd4220-a a3 56 title size document number rev date: sheet of power supply 0 akd4220-a a3 56 title size document number rev date: sheet of power supply 0 akd4220-a a3 56 agnd vvss c56 0.1u c56 0.1u r55 short r55 short l3 (short) l3 (short) c61 0.1u c61 0.1u + c60 47u + c60 47u 9 8 14 7 u7d 74lvc07 u7d 74lvc07 1 vvdd1 t45_bl vvdd1 t45_bl r56 5.1 r56 5.1 + c54 47u + c54 47u c63 0.1u c63 0.1u 11 10 14 7 u4e 74hc04 u4e 74hc04 c53 0.1u c53 0.1u jp15 dvdd jp15 dvdd jp9 reg jp9 reg + c57 47u + c57 47u + c55 (open) + c55 (open) 1 dvdd t45_o dvdd t45_o jp16 avdd jp16 avdd 5 6 14 7 u4c 74hc04 u4c 74hc04 11 10 14 7 u6e 74hc14 u6e 74hc14 5 6 14 7 u7c 74lvc07 u7c 74lvc07 1 avdd t45_r avdd t45_r 1 vvdd2 t45_bl vvdd2 t45_bl out 3 gnd 2 in 1 t1 njm78m05fa t1 njm78m05fa 1 dgnd t45_bk dgnd t45_bk + c52 47u + c52 47u 3 4 14 7 u7b 74lvc07 u7b 74lvc07 1 d5v t45_r d5v t45_r + c51 47u + c51 47u jp11 d-a jp11 d-a 1 agnd t45_bk agnd t45_bk 9 8 14 7 u6d 74hc14 u6d 74hc14 c62 0.1u c62 0.1u 1 d3.3v t45_o d3.3v t45_o jp10 vvdd1 jp10 vvdd1 13 12 14 7 u4f 74hc04 u4f 74hc04 in out gnd t2 ta48m033f t2 ta48m033f jp13 d3.3v jp13 d3.3v c50 0.1u c50 0.1u 9 8 14 7 u4d 74hc04 u4d 74hc04 r57 short r57 short 1 +12v t45_g +12v t45_g jp12 vvdd2 jp12 vvdd2 13 12 14 7 u7f 74lvc07 u7f 74lvc07 3 4 14 7 u4b 74hc04 u4b 74hc04 + c48 47u + c48 47u 13 12 14 7 u6f 74hc14 u6f 74hc14 c49 0.1u c49 0.1u + c59 47u + c59 47u l1 10u l1 10u 1 vvss t45_bk vvss t45_bk 5 6 14 7 u6c 74hc14 u6c 74hc14 l4 (short) l4 (short) 11 10 14 7 u7e 74lvc07 u7e 74lvc07
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vin1 vin2 vin3 vin4 vin5 vin6 vout1 vout2 vout3 title size document number rev date: sheet of video block input/output circuit 0 akd4220-a a3 66 title size document number rev date: sheet of video block input/output circuit 0 akd4220-a a3 66 title size document number rev date: sheet of video block input/output circuit 0 akd4220-a a3 66 r58 (short) r58 (short) r72 75 r72 75 r59 (short) r59 (short) 1 2 3 4 5 j28 vin1 j28 vin1 r60 (short) r60 (short) 1 2 3 4 5 j33 vin6 j33 vin6 c67 0.1u c67 0.1u r66 (short) r66 (short) c68 0.1u c68 0.1u r62 75 r62 75 r63 75 r63 75 r70 75 r70 75 r71 75 r71 75 1 2 3 4 5 j34 vout1 j34 vout1 r61 75 r61 75 1 2 3 4 5 j35 vout2 j35 vout2 r69 75 r69 75 1 2 3 4 5 j31 vin4 j31 vin4 1 2 3 4 5 j36 vout3 j36 vout3 1 2 3 4 5 j32 vin5 j32 vin5 r64 (short) r64 (short) c65 0.1u c65 0.1u c66 0.1u c66 0.1u r65 (short) r65 (short) c64 0.1u c64 0.1u r67 75 r67 75 c69 0.1u c69 0.1u r68 75 r68 75 1 2 3 4 5 j30 vin3 j30 vin3 1 2 3 4 5 j29 vin2 j29 vin2
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